SYZYGY Brain-1

An open-source FPGA platform
supporting Syzygy.

Features

Xilinx Zynq FPGA

1 GiB DDR3

USB Type-C OTG

3x SYZYGY Standard Ports

1x SYZYGY Transceiver Port

SD Slot

Gb Ethernet

JTAG

SYZYGY fills the gap between low speed, low pin-count Digilent PMOD devices and high-performance, high pin-count VITA 57.1 FMC peripherals.

Parameter
Port A (STD)
Port B (XCVR)
Port C (STD)
Port D (STD)

  


Port Type
  StandardTransceiverStandardStandard
Single-WidthSingle-WidthDouble-Width Capable
Total 5V Supply Current	
            2.5 A (shared with USB +5V output)
Total 3.3V Supply Current2 A shared2 A shared
VIO Supply Voltage Range1.2V to 3.3V
Total VIO Supply Current4 A (VIO Group 1)4 A (VIO Group 2)
Port GroupsGroup 1: A	Group 2: B, C, D
I/O Count28 total (8 DP)18 total	28 total (8 DP)	28 total (8 DP)
Length Matching1557 – 2055 mils
DP: ≤10 mils1079 – 1578 mils
XCVR: ≤10 mils interpair
XCVR: ≤10mils intrapair2412 – 2505 mils
DP: ≤10 mils1220 – 1309 mils
DP: ≤10 mils

Parameter	Port A (STD)	Port B (XCVR)	Port C (STD)	Port D (STD)
Port Type	Standard	Transceiver	Standard	Standard
Single-Width	Single-Width	Double-Width Capable
Total 5V Supply Current	2.5 A (shared with USB +5V output)
Total 3.3V Supply Current	2 A shared	2 A shared
VIO Supply Voltage Range	1.2V to 3.3V
Total VIO Supply Current	4 A (VIO Group 1)	4 A (VIO Group 2)
Port Groups	Group 1: A	Group 2: B, C, D
I/O Count	28 total (8 DP)	18 total	28 total (8 DP)	28 total (8 DP)
Length Matching	1557 – 2055 mils DP: ≤10 mils	1079 – 1578 mils XCVR: ≤10 mils interpair XCVR: ≤10mils intrapair	2412 – 2505 mils DP: ≤10 mils	1220 – 1309 mils DP: ≤10 mils

Note: Yes, all of these standards can go down to DC and some can go higher than we have here. This data basically illustrates what we consider to be the "sweet spot" for the interface. Your mileage may vary.

TYPICAL PERIPHERALS

Estimated price: $324.95
Available to order now via the Opal Kelly Web Store.